Stacked semiconductor package having adhesive/spacer structure and insulation

ABSTRACT

Stacked semiconductor assemblies in which a device such as a die, or a package, or a heat spreader is stacked over a first wire-bonded die. An adhesive/spacer structure is situated between the first wire-bonded die and the device stacked over it, and the device has an electrically non-conductive surface facing the first wire-bonded die. That is, the first die is mounted active side upward on a first substrate and is electrically interconnected to the substrate by wire bonding; an adhesive/spacer structure is formed upon the active side of the first die; and a device such as a die or a package or a heat spreader, having an electrically nonconductive side, is mounted upon the adhesive/spacer structure with the electrically nonconductive side facing the first wire bonded die. The side of the device facing the first wire bonded die may be made electrically nonconductive by having an electrically insulating layer, such as a dielectric film adhesive. Also, methods for making the assemblies are disclosed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation-in-Part of U.S. application Ser. No.10/969,303, filed Oct. 20, 2004, titled “Multiple die package withadhesive/spacer structure and insulated die surface”. The said U.S.application Ser. No. 10/969,303 claims priority from U.S. ProvisionalApplication No. 60/573,956, filed May 24, 2004, titled “Multiple diepackage with adhesive/spacer structure and insulated die surface”; andalso claims priority from related U.S. Provisional Application No.60/573,903, filed May 24, 2004, titled “Adhesive/spacer island structurefor multiple die package”. This application is related to U.S.application Ser. No. 10/______, Attorney Docket CPAC 1074-3, filed onthe same day as this application.

BACKGROUND

To obtain the maximum function and efficiency from a package havingminimum dimensions, various types of increased density packages havebeen developed. Among these various types of packages is themultiple-die semiconductor chip package, commonly referred to as amulti-chip module, multi-chip package or stacked chip package. Amulti-chip module includes one or more integrated circuit semiconductorchips, often referred to as circuit die, stacked one onto another toprovide the advantages of light weight, high density, and enhancedelectrical performance. To stack the semiconductor chips, each chip canbe lifted by a chip-bonding tool, which is usually mounted at the end ofa pick-and-place device, and mounted onto the substrate or onto asemiconductor chip mounted previously.

In some circumstances, such as when the upper die is smaller than thelower die and the lower die is a peripheral bonded die (that is die withbond pads positioned near the periphery of the die as opposed to acenter bonded die in which the bond pads are positioned at a centralregion of the die), the upper die can be attached directly to the lowerdie without the use of spacers. However, when spacers are needed betweenthe upper and lower die, spacer die, that is die without circuitry, canbe used between the upper and lower die. In addition, adhesivescontaining spacer elements, typically micro spheres, are often used toproperly separate the upper and lower die. See U.S. Pat. Nos. 5,323,060;6,333,562; 6,340,846; 6,388,313; 6,472,758; 6,569,709;6,593,662;.6,441,496; and U.S. patent Publication No. US 2003/0178710.

After the chip mounting process, bonding pads of the chips are connectedto bonding pads of the substrate with Au or Al wires during a wirebonding process to create an array of semiconductor chip devices.Finally, the semiconductor chips and their associated wires connected tothe substrate are encapsulated, typically using an epoxy-moldingcompound, to create an array of encapsulated semiconductor devices. Themolding compound protects the semiconductor devices from the externalenvironment, such as physical shock and humidity. After encapsulation,the encapsulated devices are separated, typically by sawing, intoindividual semiconductor chip packages.

SUMMARY

In general, the invention features stacked semiconductor assemblies inwhich a device such as a die, or a package, or a heat spreader isstacked over a first wire-bonded die. An adhesive/spacer structure issituated between the first wire-bonded die and the device stacked overit, and the device has an electrically non-conductive surface facing thefirst wire-bonded die. That is, the first die is mounted active sideupward on a first substrate and is electrically interconnected to thesubstrate by wire bonding; an adhesive/spacer structure is formed uponthe active side of the first die; and a device such as a die or apackage or a heat spreader, having an electrically nonconductive side,is mounted upon the adhesive/spacer structure with the electricallynonconductive side facing the first wire bonded die. The side of thedevice facing the first wire bonded die may be made electricallynonconductive by having an electrically insulating layer, such as adielectric film adhesive.

In one aspect the invention features a multiple-die semiconductor chipassembly. A first die has a first surface bounded by a periphery andbond pads at the first surface. Wires are bonded to and extend from thebond pads outwardly past the periphery. A second die has an electricallynon-conductive second surface positioned opposite the first surface. Thefirst and second die define a first region therebetween. Anadhesive/spacer structure, comprising spacer elements within anadhesive, is within the first region. The adhesive/spacer structurecontacts the first and second surfaces and adheres the first and seconddie to one another at a chosen separation. The assembly may comprise aset of generally parallel wires which define a wire span portion of thefirst region. The adhesive/spacer structure is preferably located atother than the wire span portion of the first region.

In another aspect the invention features a method for adhering first andsecond die to one another at a chosen separation in a multiple-diesemiconductor chip assembly. An adhesive/spacer material, having spacerelements within an adhesive, is selected. The adhesive/spacer materialis deposited onto a first surface of a first die. The first surface isbounded by a periphery and has bond pads. A set of generally parallelwires is bonded to and extends from the bond pads outwardly past theperiphery. The set of generally parallel wires define a wire spanportion of the first surface. A second die, having an electricallynon-conductive second surface, is selected. The second surface of thesecond die is located opposite the first surface of the first die and incontact with the adhesive/spacer material therebetween thereby securingthe first and second die to one another at a chosen separation, the wirespan portion of the first surface defining a wire span region betweenthe first and second surfaces. The adhesive/spacer material is depositedin a manner to prevent any spacer elements from entering the wire spanregion.

In another aspect the invention features stacked semiconductorassemblies including an upper package stacked over a first wire-bondeddie. The first die has a first surface bounded by a periphery and bondpads at the first surface. Wires are bonded to and extend from the bondpads outwardly past the periphery. An upper package has an electricallynon-conductive second surface positioned opposite the first surface ofthe first die. The first die and the upper package define a first regiontherebetween. An adhesive/spacer structure, comprising spacer elementswithin an adhesive, is within the first region. The adhesive/spacerstructure contacts the first and second surfaces and adheres the firstdie and the upper package to one another at a chosen separation. Theassembly may comprise a set of generally parallel wires which define awire span portion of the first region. The adhesive/spacer structure ispreferably located at other than the wire span portion of the firstregion.

The upper package in the stacked semiconductor assembly includes atleast one upper package die affixed to a die attach side of an upperpackage substrate. In some embodiments the upper package is oriented sothat the die attach side of the upper package substrate faces the firstdie; that is, the upper package is inverted. In other embodiments theupper package is oriented so that the side of the upper packagesubstrate opposite the die attach side faces the first die. The upperpackage may be any of a variety of package types can be suitable as theupper package.

In another aspect the invention features a method for adhering a die anda package to one another at a chosen separation in a stackedsemiconductor package. An adhesive/spacer material, having spacerelements within an adhesive, is selected. The adhesive/spacer materialis deposited onto a first surface of a first die. The first surface isbounded by a periphery and has bond pads. A set of generally parallelwires is bonded to and extends from the bond pads outwardly past theperiphery. The set of generally parallel wires define a wire spanportion of the first surface. A package, having an electricallynon-conductive second surface, is selected. The second surface of thepackage is located opposite the first surface of the die and in contactwith the adhesive/spacer material therebetween thereby securing the dieand the package to one another at a chosen separation, the wire spanportion of the first surface defining a wire span region between thefirst and second surfaces. The adhesive/spacer material is deposited ina manner to prevent any spacer elements from entering the wire spanregion.

Various features and advantages of the invention will appear from thefollowing description in which the preferred embodiments have been setforth in detail in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a simplified plan view of a conventional peripheral bondeddie;

FIG. 2 is a simplified plan view of a conventional center bonded die;

FIGS. 3 and 4 illustrate conventional forward loop and reverse wirebonds;

FIG. 5 is a partial cross sectional view of a multi-die semiconductorassembly made according to the invention;

FIG. 6 is a top plan view of the assembly of FIG. 5 with the peripheryof the upper die shown in dashed lines;

FIG. 7 illustrates an alternative embodiment to the assembly of FIG. 6;

FIG. 8 is a side cross sectional view of the assembly of FIGS. 5 and 6;

FIG. 9 shows the assembly of FIG. 8 After encapsulation with a moldingcompound to create a multiple die semiconductor chip package; and

FIG. 10 illustrates an alternative embodiment similar to that of FIG. 5in which adhesive fills the wire span portion of the adhesive region;and

FIG. 11 illustrates an alternative embodiment in a view similar to thatof FIG. 9 but in which the upper die does not overhang the edge of thelower die, and in which adhesive fills the wire span portion of theadhesive region as in FIG. 10.

FIGS. 12 through 15 illustrate embodiments of assemblies according tovarious aspects of the invention in which a package and a die arestacked.

DETAILED DESCRIPTION

The invention will now be described in further detail by reference tothe drawings, which illustrate alternative embodiments of the invention.The drawings are diagrammatic, showing features of the invention andtheir relation to other features and structures, and are not made toscale. For improved clarity of presentation, in the FIGs. illustratingembodiments of the invention, elements corresponding to elements shownin other drawings are not all particularly renumbered, although they areall readily identifiable in all the FIGs. Terms of orientation, such as“upper” and “lower” and the like are employed for reference to therelative orientation of the various features as shown in the FIGs., itbeing understood that any of the various assemblies can be deployed inany orientation in use.

Several prior art structures and embodiments made according to theinvention are discussed below. Like reference numerals refer to likeelements.

FIG. 1 illustrates a conventional peripheral bonded die 10 mounted to asubstrate 12. Die 10 has bond pads 14 along one, some or all of itsperipheral edges 16-19. Wires 20 connect bond pads 14 to correspondingbond pads 22 on substrate 12. Wires 20 comprise sets of generallyparallel wires along each peripheral edge 16-18 and define wire spanareas 24, indicated by crosshatching in FIG. 1, along such edges. Bondpads 14 on peripheral bonded die 10 are typically placed very close tothe corresponding peripheral edge 16-19, typically within 100micrometers of the peripheral edge.

FIG. 2 illustrates a conventional center bonded die 26, such as a DRAM,having bond pads 14 at a central region 28 of die 26. Wires 20 extendingfrom bond pads 14 define, in this example, wire span areas 24 betweenthe two sets of bond pads 14 and peripheral edges 16, 18. The distancebetween bond pads 14 and the corresponding peripheral edges for a centerbonded die is preferably much more than 100 micrometers. Morepreferably, the distance between a bond pad 14 for a center bonded die26 and the nearest peripheral edge is at least about 40% of thecorresponding length or width of the die. For example, the distancebetween a bond pad 14A and peripheral edge 16 is at least about 40% ofthe length of peripheral edge 17. Assuming for example that peripheraledge 17 is 8 mm long, the distance between bond pad 14A and peripheraledges 16 is at least about 3.2 mm.

FIGS. 3 and 4 illustrate conventional forward loop wire bonding andconventional reverse wire bonding techniques. Forward loop wire bond 30of FIG. 3 has a wire loop height 32, typically about 60-100 micrometers.Wire 20 has a recrystalization zone 34. Recrystalization zone 34 is notas flexible as the remainder of wire 20 so that excessive flexion ofwire 20 within zone 34 may cause wire 22 to break. Therefore, in it isimportant that wire 20, especially within recrystalization zone 34, notbe deformed to any significant degree during manufacturing. This isespecially important in the manufacture of multi-chip packages. Toreduce the loop height 32 and eliminate recrystalization zone 34 abovebond pads 14, a reverse wire bond 36, shown in FIG. 4, may be used.Reverse wire bonds 36 typically have a loop height 32 of about 40-70micrometers. Forward loop wire bonding, shown in FIG. 5, is oftenpreferred over reverse wire bonding because it has a much largerthroughput and the therefore a lower cost.

FIG. 5 illustrates a partial cross sectional view of a multi-diesemiconductor assembly 40 made according to the invention. Assembly 40includes a lower, peripheral bonded die 42 and an upper die 44. Assembly40 protects against shorting of wires 20 against upper die 44 in twobasic ways. First, upper die 44 has electrically insulating layer 45,typically a dielectric film adhesive, such as available from LintecCorporation as Lintec LE5000 or an Hitachi DF series film adhesive.Second, lower die 42, also shown in FIG. 6, is secured to upper die 44with an adhesive/spacer structure 46. Structure 46 includes adhesive 48and spacer elements 50. Structure 46 may be a conventional material suchas Loctite® QMI536-3, 4, or 6, which use nominal 3, 4 or 6 mil (75, 100and 150 micrometers) diameter organic polymer spherical particles asspacer elements 50; or a spacer adhesive from the Ablestik 2025 Sxseries. It is preferred that spacer elements 50 be of an organic polymermaterial and pliable and large enough to permit forward loop wirebonding. Spacer elements 50 are typically about 30-250 micrometers indiameter. Structure 46 also helps to provide bond line thickness controland die tilt control. Prevention of the incursion of the adhesive/spacermaterial, and in particular spacers 50, into wire span portion 60 offirst, adhesive region 58 (refer to FIG. 6) may be achieved by, forexample, depositing the adhesive/spacer material at selected positionsand carefully controlling the amount deposited at each position.Examples of suitable materials for spacer elements 50 include PTFE andother organic polymers.

Spacer elements 50, prior to use, are typically spherical, ellipsoidal,cylindrical with hemispherical or ellipsoidal ends, or the like. Afterassembly, assuming spacer elements 50 are compressible, spacer elements50 are compressed to some degree and have flattened areas where theycontact upper surface 52 of lower die 42 and the electricallynon-conductive lower surface 54 of upper die 44; the shape of suchspacers is collectively referred to as generally ellipsoidal. Forexample, an initially spherical spacer element 50 having an 8 mil (200micrometer) diameter will typically compress to a height of about 7.5mil (188 micrometers). The height 56 of spacers 50, which is equal tothe distance between surface 52 and 54, is preferably at least equal toloop height 32, is more preferably greater than loop height 32, is evenmore preferably at least about 10% greater than loop height 32. Ifdesired, the selection of the spacer elements include selecting spacerelements so that height 56 is equal to the design loop height 32 plus anallowance for manufacturing tolerance build-up resulting from making thewire bonds, the variance in the size and compressibility the of spacerelements 50 and other appropriate variables.

FIG. 6 illustrates assembly 40 with upper die 44 indicated by dashedlines. Lower and upper die 42, 44 define a first, adhesive region 58therebetween. In the embodiment of FIGS. 5 and 6, region 58 is definedby the periphery of lower die 42 because upper die 44 extends beyond theentire periphery of the lower die. Wire span areas 24, indicated bycrosshatching, define wire span portions 60 of first, adhesive region58. The adhesive/spacer material is deposited in a manner so that, asshown in FIG. 6, adhesive/spacer structure 46 is located at other thanwire span portions 60 of first, adhesive region 58. Doing so helps toensure that spacer elements 50 do not interfere with wires 20 thuseliminating the possibility of a spacer element causing one or morewires 22 to deflect to contact and thus short, for example, an adjacentwire 22.

FIG. 7 illustrates a multi-die semiconductor assembly 62 in which lowerdie 42 is a center bonded die such as shown in FIG. 2 and upper die 44,shown in dashed lines, is longer but narrower than lower die 42.Therefore, in this embodiment first, adhesive region 58 does not coverthe entire lower die 42 but rather is bounded by peripheral edges 17 and19 of lower die 42 and peripheral edges 16 and 18 of upper die 44.Adhesive/spacer structure 46 is, in the embodiment of FIG. 6, locatedwithin first, adhesive region 58 at other than wire span portions 60.Adhesive/spacer structure 46 may define a single adhesive/spacerstructure region as shown in FIG. 6 or two or more adhesive/spacerstructure regions, such as shown in FIG. 7.

Adhesive/spacer material may be deposited using a conventional dispensercapillary. However, it is preferred that the adhesive/spacer material bedeposited using a showerhead type of dispenser as shown in theabove-mentioned US Provisional Patent Application entitledAdhesive/Spacer Island Structure For Multiple Die Package. Doing so canfacilitate the positioning of the adhesive/spacer material at spacedapart locations to provide the desired coverage by adhesive/spacerstructure 46. This may be especially advantageous when working withcenter bonded die.

FIG. 8 is a side cross sectional view of multi-die semiconductorassembly 40 of FIGS. 5 and 6 showing wires 20 extending from bond pads14 of upper and lower die 44, 42 to bond pads 22 of substrate 12. FIG. 9illustrates the structure of FIG. 8 after a molding compound 66 has beenapplied to create a multiple die semiconductor chip package 68.

Spacer elements 50 may also be prevented from incursion into wire spanportion 60 by sizing the spacer elements so as not to fit between thegenerally parallel wires 20. In this way wires 20 act as a sieve orstrainer to permit a portion 47 of adhesive 48 to enter into wire spanportion 60 but prevent spacer elements 50 from doing so. This isillustrated in FIG. 10, showing adhesive/spacer structure 46 includingadhesive 48, with spacer elements 50 situated in regions other than thewire span portion of the adhesive region, and showing a portion 47 ofadhesive 48 having entered into the wire span portion of the adhesiveregion. In such embodiments, the spacer elements provide a suitabledistance between the two die, the lower surface of the upper die beingelectrically insulated by dielectric layer 45, as described above withreference to FIG. 5. The full occupancy of adhesive region 58 byadhesive 48, particularly the portion 47 of the adhesive in the wirespan region, eliminates the open overhang of the upper die above wires20 shown in FIG. 5. This provides some support for the upper die, andhelps to reduce or eliminate die breakage, which is especially usefulfor large and thin semiconductor devices.

The adhesive/spacer structure according to the invention can be usefulfor multi-die assembly structures in which the upper die 44 does notextend over the edge of the lower die 42, as illustrated in FIG. 11,which is a view similar to the view of FIG. 9. Here, as in FIG. 10,spacer structure 46 including spacer elements 50 and adhesive 48 isformed between the upper die 44 with insulating layer 45, and the lowerdie 42. The wires 20 prevent the spacer elements from entering into thewire span region, but permit a portion 47 of the adhesive 48 to fill thevolume there and provide support for the part of the upper 44 die thatoverhangs the wire loops 20.

In other embodiments, a stacked semiconductor assembly includes apackage stacked with a die, separated by an adhesive/spacer materialgenerally as described above for stacked die assemblies. FIGS. 12 and 13illustrate examples 102, 103 of such assemblies, in which an invertedpackage is stacked over a die. Referring to FIG. 12, a lower, peripheralbonded die 142 is mounted upon a substrate 112, and bond pads on the dieare electrically interconnected with bond pads on the substrate by wirebonds 120. An adhesive/spacer structure 146 is formed upon the die 142including an adhesive and spacer elements as described above withreference to adhesive/spacer structure 46. An upper package 100 isinverted and mounted upon the adhesive/spacer structure 146, insubstantially the same manner as the upper die 44 is mounted uponadhesive/spacer structure 46 in the stacked die assembly 40, forexample, of FIG. 8.

The upper package 100 in this example is a land grid array package,having a die 242 mounted onto a die attach side on upper packagesubstrate 112. Die 242 in this example is wire bonded to substrate 112,and the die and wire bonds are enclosed in an encapsulation 217. Thepackage 100 is inverted so that the land side of the substrate 212 facesaway from the first die 142 and substrate 212, and so that an uppersurface of the encapsulation 217 faces toward the first die 142 andsubstrate 212. In the orientation of FIG. 12, the land side of theinverted upper package 212 is upward-facing, and the upper package iselectrically interconnected with the bottom substrate 212 by wire bondsbetween bond pads on the land side of the upper package substrate 212and bond pads on the upward-facing side of the lower substrate 112. Theassembly is then encapsulated (not shown in FIG. 12) to form a package,substantially as the stacked die assembly 40 of FIG. 8 is encapsulatedto form the package 68 of FIG. 9. Solder balls 118 are mounted onto padson the downward-facing side of the substrate 112, for interconnection ofthe package to, for example, a motherboard. Multiple chip modules havinginverted package stacked over a die, in which the adhesive/spacerstructures described herein may be particularly suitable, are describedin U.S. patent application Ser. No. 11/014,257.

In other embodiments, two (or more) die may be stacked using anadhesive/spacer structure over one another on a lower substrate, and apackage may be stacked over the uppermost one of the stacked die, usingan adhesive/spacer structure, as shown by way of example in FIG. 13.Here, a die 142 is mounted onto a lower substrate 112, and a die 144 isstacked over the die 142, and separated from it by an adhesive/spacerstructure 246 as described above for stacked die assemblies. Die 142 and144 are electrically interconnectedd with substrate 112 by wire bonds220. An inverted pachage 100 is mounted over the stacked die 142, 144,separated by the die 144 by and adhesive/spacer structure 246, asdescribed above with reference to FIG. 12. As will be appreciated,either or both of the spacers, between the die, and between the die andthe inverted package, may be an adhesive/spacer structre as describedabove with referenbce to stacked die assemblies.

Any of a variety of packages may be stacked over the die in assembliesaccording to these embodiments of the invention. Stacked multi-packagemodules having inverted upper packages are described in U.S. patentapplication Ser. No. 10/681,572; and examples of suitable upper invertedpackage types are described therein. These include, for example, besidesland grid array packages as illustrated in FIGS. 12 and 13, bump chipcarrier packages; and the upper package may include more than one die.Where the upper package encapsulant has a generally planar surface thatcontacts the adhesive/spacer structure, that surface (termed the“second” surface) is itself electrically nonconductive, and applicationof an additional insulating layer (as layer 45 in FIGS. 5, 8, 10 and 11)may be optional in such embodiments. Where, however, the second surfaceof the upper package is an electrically conductive material (such as ametal heat spreader, for example) or includes exposed electricallyconductive areas or elements, an insulating layer 45 should be applied,as described above with reference for example to FIG. 5.

In still other embodiments, in which a stacked semiconductor assemblyincludes a package stacked with a die, separated by an adhesive/spacermaterial generally as described above for stacked die assemblies, theupper package is not inverted. FIGS. 14 and 15 illustrate examples 104,104 of such assemblies. Referring to FIG. 14, a lower, peripheral bondeddie 142 is mounted upon a substrate 112, and bond pads on the die areelectrically interconnected with bond pads on the substrate by wirebonds 120. An adhesive/spacer structure 146 is formed upon the die 142including an adhesive and spacer elements as described above withreference to adhesive/spacer structure 46. An upper package 400 isinverted and mounted upon the adhesive/spacer structure 146, insubstantially the same manner as the upper die 44 is mounted uponadhesive/spacer structure 46 in the stacked die assembly 40, forexample, of FIG. 8.

The upper package 400 in this example is a land grid array package,having a die 442 mounted onto a die attach side on upper packagesubstrate 412. Die 442 in this example is wire bonded to substrate 412,and the die and wire bonds are enclosed in a mold cap 417. Here thepackage 400 is oriented so that the land side of the substrate 412 facestoward the first die 142 and substrate 212, and so that the land side ofthe upper package substrate 412 faces toward the first die 142 andsubstrate 212. In the orientation of FIG. 14, the land side of theinverted upper package 412 is downward-facing, and the upper package iselectrically interconnected with the bottom substrate 112 by wire bondsbetween bond pads on the upward-facing (die attach) side of the upperpackage substrate 412 and bond pads on the upward-facing side of thelower substrate 112. The assembly is then encapsulated (not shown inFIG. 14) to form a package, substantially as the stacked die assembly 40of FIG. 8 is encapsulated to form the package 68 of FIG. 9. Solder balls118 are mounted onto pads on the downward-facing side of the substrate112, for interconnection of the package to, for example, a motherboard.

In other embodiments, two (or more) die may be stacked using anadhesive/spacer structure over one another on a lower substrate, and apackage may be stacked over the uppermost one of the stacked die, usingan adhesive/spacer structure, as shown by way of example in FIG. 15.Here, as in FIG. 13, a die 142 is mounted onto a lower substrate 112,and a die 144 is stacked over the die 142, and separated from it by anadhesive/spacer structure 246 as described above for stacked dieassemblies. Die 142 and 144 are electrically interconnectedd withsubstrate 112 by wire bonds 220. An inverted pachage 100 is mounted overthe stacked die 142, 144, separated by the die 144 by andadhesive/spacer structure 246, as described above with reference to FIG.14. As will be appreciated, either or both of the spacers, between thedie, and between the die and the inverted package, may be anadhesive/spacer structre as described above with referenbce to stackeddie assemblies.

Any of a variety of packages may be stacked over the die in assembliesaccording to these embodiments of the invention. Stacked multi-packagemodules suitable upper packages are described in U.S. patentapplications Ser. Nos. 10/632,549; 10/632,568; 10/632,551; 10/632,552;10/632,553; and 10/632,550; and examples of suitable upper package typesare described therein. These include, for example, besides land gridarray packages as illustrated in FIGS. 14 and 15, bump chip carrierpackages, and flip chip packages; and the upper package may include morethan one die. Where the downward-facing surface of the upper package(“second” surface) had electrically conductive elements or areas,application of an additional insulating layer (as layer 45 in FIGS. 5,8, 10 and 11) may be required and may be applied as described above withreference for example to FIG. 5, and as shown for example at 450 inFIGS. 14 and 15. This additional insulating layer may be applied as afilm to the land side of the upper package substrate, and voids betweenthe film and the substrate surface removed by heating at low pressure,according to techniques known in the art.

Other devices may be stacked over the first die, and separated therefromby an adhesive/spacer structure as described above, and provided with aninsulating layer as appropriate. For example, a metal heat spreader maybe stacked upon an adhesive/spacer structure over the first die in placeof the upper die or upper package in the descriptions above.

The assemblies and packages according to the invention can be useful inany of a variety of products, such as for example computers, mobiletelecommunications devices, personal digital assistance devices, mediastorage devices, particularly portable cameras and audio and videoequipment.

Any and all patents, patent applications and printed publicationsreferred to above are incorporated by reference.

Other modification and variation can be made to the disclosedembodiments without departing from the subject of the invention asdefined in following claims.

1. A multiple-die semiconductor chip package comprising: a first diehaving a first surface bounded by a periphery and having bond pads atthe first surface; wires bonded to and extending from the bond padsoutwardly past the periphery, the wires extending to a maximum height habove the first die; a second die with an electrically non-conductivesecond surface positioned opposite the first surface; the first andsecond die defining a first region therebetween; an adhesive/spacerstructure within the first region, the adhesive/spacer structurecontacting the first and second surfaces and adhering the first andsecond die to one another at a chosen separation, the adhesive/spacerstructure comprising spacer elements within an adhesive.
 2. The packageaccording to claim 1 wherein the wires comprise a plurality of sets ofgenerally parallel wires, said plurality of sets of generally parallelwires defining a plurality of wire span portions of the first region. 3.The package according to claim 1 wherein the wires comprise a set ofgenerally parallel wires, said set of generally parallel wires defininga wire span portion of the first region.
 4. The package according toclaim 3 wherein the adhesive/spacer structure is located at other thanthe wire span portion of the first region.
 5. The package according toclaim 4 wherein said adhesive is located at the wire span portion of thefirst region.
 6. The package according to claim 5 wherein the spacerelements are sized so as not to fit between the generally parallelwires.
 7. The package according to claim 3 wherein the spacer elementsare located at other than the wire span portion of the first region. 8.The package according to claim 1 wherein the adhesive/spacer structuredefines first and second spaced-apart adhesive/spacer structure regions.9. The package according to claim 1 wherein the first die has a lengthand a width and a central region.
 10. The package according to claim 9wherein the first die comprises a center-bonded die with at least someof said die pads positioned at the central region.
 11. The packageaccording to claim 10 wherein at least one of the spacer elements ispositioned within the central region.
 12. The package according to claim1 wherein the spacer elements have a height H with H being at leastabout equal to h.
 13. The package according to claim 12 wherein H isgreater than h.
 14. The package according to claim 12 wherein H is atleast about 10% greater than h.
 15. The package according to claim 1wherein the spacer elements are generally ellipsoidal.
 16. The packageaccording to claim 15 wherein the spacer elements are flattened spheres.17. The package according to claim 15 wherein the spacer elements areabout 30 μm-250 μm in diameter.
 18. The package according to claim 1wherein the spacer elements are all substantially the same size.
 19. Thepackage according to claim 1 wherein the spacer elements comprise anorganic and pliable solid material.
 20. The package according to claim 1wherein the spacer elements comprise at least PTFE.
 21. A method foradhering first and second die to one another at a chosen separation in amultiple-die semiconductor chip package, the method comprising:selecting an adhesive/spacer material having spacer elements within anadhesive; depositing the adhesive/spacer material onto a first surfaceof a first die, the first die having a first surface bounded by aperiphery, bond pads at the first surface, and wires bonded to andextending from the bond pads outwardly past the periphery, the wiresextending to a maximum height h above the first die, the wirescomprising a set of generally parallel wires, the set of generallyparallel wires defining a wire span portion of the first surface;selecting a second die having an electrically non-conductive secondsurface; locating the second surface of the second die opposite thefirst surface of the first die and in contact with the adhesive/spacermaterial therebetween thereby securing the first and second die to oneanother at a chosen separation, the wire span portion of the firstsurface defining a wire span region between the first and secondsurfaces; and preventing any spacer elements from entering the wire spanregion.
 22. The method according to claim 21 further comprisingpreventing any adhesive/spacer material from entering the wire spanregion.
 23. The method according to claim 21 wherein the preventing stepcomprises using spacer elements sized so as not to fit between thegenerally parallel wires.
 24. The method according to claim 21 whereinthe depositing step is carried out a manner to prevent anyadhesive/spacer material from entering the wire span region.
 25. Themethod according to claim 21 wherein the selecting step is carried outto select spacer elements having the same size and shape.
 26. The methodaccording to claim 21 wherein the depositing step is carried out withthe first die having a length and a width and a central region.
 27. Themethod according to claim 26 wherein the depositing step is carried outwith the first die comprising a center-bonded die with at least some ofsaid die pads positioned at the central region.
 28. The method accordingto claim 27 wherein depositing step comprises positioning at least someof the adhesive/spacer material within the central region so that atleast one spacer element is positioned within the central region. 29.The method according to claim 21 wherein the adhesive/spacer materialselecting step comprises selecting spacer elements having a height Hwith H being at least about equal to h.
 30. The method according toclaim 29 wherein the spacer elements selecting step comprises selectingspacer elements in which H is greater than h.
 31. The method accordingto claim 29 wherein the spacer elements selecting step comprisesdetermining an allowance for manufacturing tolerance buildup andselecting spacer elements so that H is equal to h plus the allowance forthe manufacturing tolerance buildup.
 32. The method according to claim29 wherein the spacer elements selecting step comprises determining anallowance for manufacturing tolerance buildup and selecting spacerelements so that H is greater than h plus the allowance for themanufacturing tolerance buildup.
 33. The method according to claim 29wherein the spacer elements selecting step comprises selecting spacerelements so that H is at least about 10% greater than h.
 34. A stackedsemiconductor assembly comprising: a first die having a first surfacebounded by a periphery and having bond pads at the first surface; wiresbonded to and extending from the bond pads outwardly past the periphery,the wires extending to a maximum height h above the first die; apackage, comprising a package die mounted to and electricallyinterconnected with a package substrate, the package having anelectrically non-conductive second surface positioned opposite the firstsurface; the first die and the package defining a first regiontherebetween; an adhesive/spacer structure within the first region, theadhesive/spacer structure contacting the first and second surfaces andadhering the first die and the package to one another at a chosenseparation, the adhesive/spacer structure comprising spacer elementswithin an adhesive.
 35. The stacked semiconductor assembly of claim 34wherein the upper package is oriented so that the die attach side of theupper package substrate faces the first die.
 36. The stackedsemiconductor assembly of claim 34 wherein the upper package is orientedso that side of the upper package substrate opposite the die attach sidefaces the first die.
 37. Stacked semiconductor packages comprising theassembly of claim
 34. 38. A method for adhering a die and a package toone another at a chosen separation in a stacked semiconductor package,the method comprising: Selecting an adhesive/spacer material havingspacer elements within an adhesive; depositing the adhesive/spacermaterial onto a first surface of a first die, the first die having afirst surface bounded by a periphery, bond pads at the first surface,and wires bonded to and extending from the bond pads outwardly past theperiphery, the wires extending to a maximum height h above the firstdie, the wires comprising a set of generally parallel wires, the set ofgenerally parallel wires defining a wire span portion of the firstsurface; Selecting a package having an electrically non-conductivesecond surface; locating the second surface of the package opposite thefirst surface of the first die and in contact with the adhesive/spacermaterial there between thereby securing the package and the first die toone another at a chosen separation, the wire span portion of the firstsurface defining a wire span region between the first and secondsurfaces; and Preventing any spacer elements from entering the wire spanregion.